/***********************************************************************
2010-2011 (C) Alex Dobrianski Luna modem/Communication module based on 24L01
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see
************************************************************************/
#define Clock_8MHz
#define Baud_9600
//#define Baud_19200
#define bitset(i,j) i |= 1U << j
#define bitclr(i,j) i &= ~(1U << j)
#define bittest(i,j) (i & (1U< // Required to interface with delay routines
#ifndef _XTAL_FREQ
// Unless already defined assume 4MHz system frequency
// This definition is required to calibrate __delay_us() and __delay_ms()
#define _XTAL_FREQ 8000000
#endif
#include "stdio.h"
#define delay_ms __delay_ms
// for hi_tech c needs to have
#else
//There is no config word because this program tested on a 16F88 using Bloader the boot load program
#pragma origin 4
#pragma codeLevel 1
#pragma optimize 1
#include "inline.h"
//#include "Delay_m.c" // Delays
//#include "Stdio.c" // Basic Serial IO
//#define putch rs_out
// RB5 - Serial Out Pin 11
// RB2 - Serial In Pin 8
void enable_uart()//bit want_ints)
{
TX9 = 0;
RX9 = 0;
BRGH = 1; //Normal speed UART port 0x98
// 00000x00 BRGH: High Baud Rate Select bit
//Asynchronous mode:
// 1 = High speed 0 = Low speed
switch(Config01 & 0x03)
{
case 0:SPBRG = 51;break;
case 1:SPBRG = 25;break;
case 2:SPBRG = 12;break;
case 3:SPBRG = 8;break;
}
//SPBRG = 51;//207;//51; // 9600 for 8MH
SYNC = 0; // port 0x98 = 000x0000 x=0 asynch mode 1-synchr
SPEN = 1; // port 0x18 x0000000 SPEN: Serial Port Enable bit
// 1 = Serial port enabled (configures RB2/SDO/RX/DT
// and RB5/SS/TX/CK pins as serial port pins)
//if(want_ints) //Check if we want to turn on interrupts
//{
// TXIE = 1;
// PEIE = 1;
// GIE = 1;
//}
TXEN = 1; //Enable transmission port 0x8c
// AUSART Transmit Interrupt Enable bit
// 1 = Enabled 0 = Disabled
ADDEN = 0;
CREN = 1; // port 0x18 000x0000 CREN: Continuous Receive Enable bit
// Asynchronous mode: 1 = Enables continuous receive
SecondByte = 0;
//WREN = 1;
}
void putch(unsigned char nate)
{
TXREG = nate; // port 0x19
while(TXIF == 0); // port 0x0c 000x0000 TXIF:
// AUSART Transmit Interrupt Flag bit
// 1 = The AUSART transmit buffer is empty
// (cleared by writing to TXREG)
}
void puts(const char * s)
{
while(*s)
{
putch(*s);
s++;
}
}
#endif
#define PORT_TX PORTA
#define PORT_RX PORTA
#ifdef _RF2401A
#define Tx_CE 0 // RA0 pin 17 // Chip Enable Activates RX or TX mode
#define Tx_CS 1 // RA1 pin 18 // Chip Select Activates Configuration Mode
#define Tx_CLK 3 // RA3 pin 2 // Clock Input (TX) & Output/Input (RX) for Data Channel 1
// 3-wire interface
#define Tx_DAT 4 // RA4 pin 3 // RX Data Channel 1/TX Data Input/ 3-wire interface
#define Rx_CE 0 // RA0 pin 17 // Chip Enable Activates RX or TX mode
#define Rx_CS 1 // RA1 pin 18 // Chip Select Activates Configuration Mode
#define Rx_CLK 3 // RA3 pin 2 // Clock Input (TX) & Output/Input (RX) for Data Channel 1
// 3-wire interface
#define Rx_DAT 4 // RA4 pin 3 // RX Data Channel 1/TX Data Input/ 3-wire interface
#define Rx_DR1 2 // RA2 pin 1 // RX Data Ready at Data Channel 1 (ShockBurst™ only)
#else
#define Tx_CE 0 // RA0 pin 17 // Chip Enable Activates RX or TX mode
#define Tx_CSN 1 // RA1 pin 18 // SPI Chip Select
#define Tx_SCK 2 // RA2 pin 1 // SPI Clock
#define Tx_MOSI 3 // RA3 pin 2 // SPI Slave Data Input
#define Rx_MISO 4 // RA4 pin 3 // SPI Slave Data Output, with tri-state option
#define Rx_IRQ 7 // RA7 pin 16 // Maskable interrupt pin. Active low
#endif
//#include // Required to interface with delay routines
//There is no config word because this program tested on a 16F88 using Bloader the boot load program
//#define TX_CE PORTB.0
//#define TX_CE (PORTB&0b00000001)
//#define TX_CS PORTB.1
//#define TX_CS (PORTB&0b00000010)
//#define TX_CLK1 PORTB.3
//#define TX_CLK1 (PORTB&0b00001000)
//#define TX_DATA PORTB.4
//#define TX_DATA (PORTB&0b00010000)
//#define RX_CE PORTA.2
//#define RX_CE (PORTA&0b00000100)
//#define RX_CS PORTA.3
//#define RX_CS (PORTA&0b00001000)
//#define RX_CLK1 PORTA.4
//#define RX_CLK1 (PORTA&0b00010000)
//#define RX_CLK1_SET_1 (PORTA|=0b00010000)
//#define RX_CLK1_SET_0 (PORTA&=0b11101111)
//#define RX_DATA PORTA.1
//#define RX_DATA (PORTA&0b00000010)
//#define RX_DR PORTA.0
//#define RX_DR (PORTA&0b00000001)
//unsigned char data_array[MAX_MESSAGE];//29];
#pragma rambank 1
unsigned char TX_data_array[MAX_MESSAGE];//29];
unsigned char TX_data_len;
unsigned char RX_data_array[MAX_MESSAGE_PLUS_PLUS];//29];
unsigned char RX_data_len;
unsigned char RX_data_out;
#pragma rambank 0
// Delays a multiple of 8 mikroseconds at 8 MHz
// using the TMR0 timer
void delay_mks( unsigned char miks)
{
unsigned char next = miks;
OPTION = 3; // prescaler divide TMR0 rate by 8 for 8 MHz it will be 8mks (or 16 cicles)
TMR0 = 0;
while (TMR0 != next) // x* 8 mks
{
}
}
unsigned char eeprom_read(unsigned char addr)
{
EEADR = addr;
EECON1 &= 0x3F;
RD = 1;
return EEDATA;
}
void eeprom_write(unsigned char addr, unsigned char value)
{
EEADR = addr;
EEDATA = value;
EECON1 &= 0x3F;
Carry = 0;
if(GIE)
Carry = 1;
GIE = 0;
WREN = 1;
EECON2 = 0x55;
EECON2 = 0xAA;
WR = 1;
WREN = 0;
if(Carry)
GIE = 1;
while(WR)
{
}
}
void Reset_device(void);
void configure_receiver(void);
void configure_transmitter(void);
void transmit_data(void);
void receive_data(void);
void configure_common(void);
unsigned char GetCD(void);
unsigned char AtBegin;
bit DataMode;
bit ATE0;
bit flOut2rs232;
//bit flGetCD;
void AddByteToTransmit(unsigned char Rs232byte)
{
TX_data_array[TX_data_len] = Rs232byte;
TX_data_len++;
if (TX_data_len >= msTxlen)
{
configure_transmitter();
transmit_data();
configure_receiver();
TX_data_len = 0;
}
}
void main()
{
//unsigned char i;
//unsigned int elapsed_time;
unsigned char Rs232byte = 0;
unsigned char CounterPluses = 0;
unsigned char DelayCounter;
bit GetRing = 0;
ATE0 = 1;
DataMode = 0;
AtBegin = 0;
flOut2rs232 = 1;
TX_data_len = 0;
RX_data_len = 0;
RX_data_out = 0;
DelayCounter = 0;
Reset_device();
puts("\n\rLunaB modem\n\rOK\n\r");
#ifdef _RF2401A
// 1. Correct address and size of payload of incoming RF packages are set when
// nRF2401A is configured to ShockBurst™ RX.
// 2. To activate RX, set CE high.
// 3. After 200 µs settling, nRF2401A is monitoring the air for incoming
// communication.
// 4. When a valid package has been received (correct address and CRC found),
// nRF2401A removes the preamble, address and CRC bits.
// 5. nRF2401A then notifies (interrupts) the MCU by setting the DR1 pin high.
bitset(PORT_RX,Rx_CE);//RX_CE = 1;
#else
#endif
while (1)//Rs232byte != 'Q')
{
#ifdef _RF2401A
if(bittest(PORT_RX,Rx_DR1)) //We have data!
{
receive_data();
}
#else
if (bittest(Config01, 4)) //Carrier detection // ats9=lun040112233
{
//GetCD();
//if (flGetCD)
if (GetCD())
{
receive_data();
}
}
else
{
if (bittest(PORT_RX,Rx_IRQ)==0) //wait air for something
{
receive_data();
}
}
#endif
//Rs232byte = 0;
//Rs232byte = getch();
//if (Rs232byte)
if (RCIF != 0)
{
Rs232byte = RCREG;
DelayCounter = 0;
if (ATE0)
putch(Rs232byte);
if (DataMode == 1)
{
if (Rs232byte == '+')
{
CounterPluses++;
if (CounterPluses >= 3)
{
DataMode = 0;
CounterPluses = 0;
puts("\n\rOK\n\r");
}
}
else
{
while(CounterPluses)
{
AddByteToTransmit('+');
CounterPluses--;
}
AddByteToTransmit(Rs232byte);
}
}
else
{
if (Rs232byte == 0x0d)
{
//bitclr(PORTB,1);
if (AtBegin >= 2)
{
switch(AtBegin)
{
case 5: case 7:
puts("\n\rCONNECT ");
switch(Config01 & 0x03)
{
case 0:puts("9600\n\r");break;
case 1:puts("19200\n\r");break;
case 2:puts("38400\n\r");break;
case 3:puts("57600\n\r");break;
}
DataMode = 1;
TX_data_len = 0;
CounterPluses = 0;
break;
case 6:
DataMode = 0;
break;
case 21:
Reset_device();
break;
}
puts("\n\rOK\n\r");
}
AtBegin = 0;
}
switch(AtBegin)
{
case 0:
if ((Rs232byte == 'a') || (Rs232byte == 'A'))
AtBegin = 1;
break;
case 1:
if ((Rs232byte == 't') || (Rs232byte == 'T'))
AtBegin = 2;
break;
case 2:
switch(Rs232byte)
{
case 'e': case 'E': AtBegin = 3; break;
case 'd': case 'D': AtBegin = 5; break;
case 'h': case 'H': AtBegin = 6; break;
case 'a': case 'A': AtBegin = 7; break;
case 's': case 'S': AtBegin = 8; break;
}
break;
case 3:
if (bittest(Rs232byte,0))
ATE0 = 1;
else
ATE0 = 0;
AtBegin = 4;
break;
case 8:
if (Rs232byte == '=') // ATS9=
AtBegin = 9;
break;
case 9:case 10:case 11: // Address ATS9=Lun
eeprom_write(0x34-9 + AtBegin, Rs232byte);
AtBegin++;
break;
case 12: // baud rate ATS9=Lun0
// 0=9600 1=19200 2=38400 3=57600
Rs232byte &= 0x3; Config01 &= 0xfc;
Config01 |= Rs232byte;
AtBegin++;
break;
case 13: // mode ATS9=Lun00
Rs232byte &= 0x7; Rs232byte <<=2; Config01 &= 0xe3;
Config01 |= Rs232byte;
AtBegin++;
break;
case 14: // ATS9=Lun000
// basic communication using carrier detection
// transfer all recived to computer
// one bit reserved
Rs232byte &= 0x7; Rs232byte <<=5; Config01 &= 0x1f;
Config01 |= Rs232byte;
eeprom_write(0x30, Config01);
AtBegin++;
break;
case 15: // 1 channel ATS9=Lun00002
//Rs232byte &= 0x0f; Rs232byte <<=4;
Freq1 = Rs232byte & 0x0f;
AtBegin++;
break;
case 16:
//Rs232byte &= 0x0f; Freq1 &= 0xf0;
Freq1 |= (Rs232byte & 0x0f);
eeprom_write(0x31, Freq1);
AtBegin++;
break;
case 17: // 2 channel ATS9=Lun0000203
//Rs232byte &= 0x0f; Rs232byte <<=4;
Freq2 = Rs232byte & 0x0f;
AtBegin++;
break;
case 18:
//Rs232byte &= 0x0f; Freq2 &= 0xf0;
Freq2 |= (Rs232byte & 0x0f);
eeprom_write(0x32, Freq2);
AtBegin++;
break;
case 19: // 3 channel ATS9=Lun000020304
//Rs232byte &= 0x0f; Rs232byte <<=4;
Freq3 = Rs232byte & 0x0f;
AtBegin++;
break;
case 20:
//Rs232byte &= 0x0f; Freq3 &= 0xf0;
Freq3 |= (Rs232byte & 0x0f);
eeprom_write(0x33, Freq3);
AtBegin++;
break;
}
}
}
else
{
if (RX_data_out != RX_data_len)
{
// needs to output message from a buffer
//TXREG = data;
//while(TXIF == 0);
if (TXIF == 0) // wait for next byte ready to transmit
{
}
else
{
if (RX_data_array[RX_data_out] != 0xff)
{
TXREG = RX_data_array[RX_data_out];
}
RX_data_out++;
if (RX_data_out >= (msRxlen+1))//MAX_MESSAGE_PLUS)
RX_data_out = 0;
}
}
else
{
if (bittest(RCSTA,2))
{
CREN =0;
CREN =1;
}
}
DelayCounter++;
if (DelayCounter >=0xfe)
{
if (TX_data_len > 0)
{
for (DelayCounter = TX_data_len; DelayCounter < msTxlen; DelayCounter++)
{
AddByteToTransmit(0xff);
}
}
DelayCounter = 0;
}
}
}
}
void Reset_device(void)
{
unsigned char bTemp;
OSCCON = 0b01110000; //Setup internal oscillator for 8MHz
while((OSCCON&0b00000100) == 0); //Wait for frequency to stabilize
// delay_ms(10);
ANSEL = 0b00000000; //Turn pins to Digital instead of Analog
CMCON = 0b00000111; //Turn off comparator on RA port
#ifdef _RF2401A
PORTA = 0b00000000;
//TRISA = 0b00000100; //0 = Output, 1 = Input (RX_DR is on RA0)
TRISA = (1U << Rx_DR1);
#else
PORTA = 0b00000000;
//TRISA = 0b00000100; //0 = Output, 1 = Input (RX_DR is on RA0)
TRISA = (1U << Rx_MISO) | (1U << Rx_IRQ);
#endif
// RB5 - Serial Out Pin 11
// RB2 - Serial In Pin 8
PORTB = 0b00000000;
TRISB = 0b00000100; //0 = Output, 1 = Input
Config01 = eeprom_read(0x30);
Freq1 = eeprom_read(0x31);
Freq2 = eeprom_read(0x32);
Freq3 = eeprom_read(0x33);
Addr1 = eeprom_read(0x34);
Addr2 = eeprom_read(0x35);
Addr3 = eeprom_read(0x36);
if ((Config01 == 0xff) && (Freq1 == 0xff))
{
Config01 = 0;
Freq1 = 2;
Freq2 = 3;
Freq3 = 4;
Addr1 = 'L';
Addr2 = 'u';
Addr3 = 'n';
}
msTxlen = MAX_MESSAGE;
msRxlen = MAX_MESSAGE;
switch(Config01&0x1c)
{
case 0x00: // '0' = 0 - 250kbit check sum 2 bytes
break;
case 0x04: // '1' = 1 - 250kbit; no check sum on receive (on transmit yes)
// because of this needs to read extra 2 bytes
break;
case 0x08: // '2' = 2 - 250kbit; no chek sum on receive, 3 bit in one one
// total payload 10 bytes converted to 30
msTxlen = 10;
msRxlen = 10;
break;
case 0x0c: // '3' = 3 - 250kbit; no check sum on receive, 5 bit in one one
// total payload 6 bytes converted to 30 bytes
msTxlen = 6;
msRxlen = 6;
break;
case 0x10: // '4' = 4 - carrier detection
// total payload 8 bytes with parity bit
msTxlen = 8;
msRxlen = 8;
break;
}
//flGetCD = 0;
#ifdef HI_TECH_C
#else
enable_uart(); //Setup the hardware UART for 20MHz at 9600bps
//enable_uart_TX(0);
//enable_uart_RX(0); //Take a look at header files - it's not that hard to setup the UART
//printf("\n\rRF-24G Testing:\n\r", 0);
//delay_ms(1);//00);
#endif
// configure_transmitter();
// configure_receiver();
configure_common();
configure_receiver();
//putch(0x30| (Freq1>>4));
//putch(0x30| (0x0f&Freq1));
}
#ifdef _RF2401A
//This will clock out the current payload into the data_array
void receive_data(void)
{
unsigned char i, j, temp;
// 6. MCU may (or may not) set the CE low to disable the RF front end (low
// current mode).
// 7. The MCU will clock out just the payload data at a suitable rate (ex. 10
// kbps).
// 8. When all payload data is retrieved nRF2401A sets DR1 low again, and is
// ready for new incoming data package if CE is kept high during data
// download. If the CE was set low, a new start up sequence can begin, see
// Figure 16.
//RX_CE = 0;
bitclr(PORT_RX,Rx_CE);//Power down RF Front end
// set TRISA to input
bitset(TRISA, Tx_DAT);
//Erase the current data array so that we know we are looking at actual received data
//for(i = 0 ; i < MAX_MESSAGE ; i++)
// data_array[i] = 0x00;
//Clock out the data
for(i = 0 ; i < MAX_MESSAGE ; i++) //29 bytes
{
for(j = 0 ; j < 8 ; j++) //8 bits each
{
temp <<= 1;
//temp.0 = RX_DATA;
if (bittest(PORT_RX, Rx_DAT))
bitset(temp,0);
bitset(PORT_RX,Rx_CLK);//RX_CLK1 = 1;
bitclr(PORT_RX,Rx_CLK);//RX_CLK1 = 0;
}
//data_array[i] = temp; //Store this byte
putch(temp);
}
//if(RX_DR == 0) //Once the data is clocked completely, the receiver should make DR go low
// printf("DR went low\n\r", 0);
//// printf("Received packet %d\n\r", data_array[0]);
//This prints out the entire array - very large!
/*
printf("\n\rData Received:\n\r", 0);
for(i = 0 ; i < 29 ; i++)
{
printf("[%d]", i);
printf(" : %h - ", data_array[i]);
}
*/
bitset(PORT_RX,Rx_CE);//RX_CE = 1; //Power up RF Front end
}
//This sends out the data stored in the data_array
//data_array must be setup before calling this function
void transmit_data(void)
{
unsigned char i, j, temp, rf_address;
// 1. When the application MCU has data to send, set CE high. This activates
// nRF2401A on-board data processing.
bitset(PORT_TX,Tx_CE);//TX_CE = 1;
// set TRISA to output
bitclr(TRISA, Tx_DAT);
//Clock in address
rf_address = 17;
for(i = 0 ; i < 8 ; i++)
{
//TX_DATA = rf_address.7;
if (rf_address & 0x80)
bitset(PORT_TX, Tx_DAT);
else
bitclr(PORT_TX, Tx_DAT);
bitset(PORT_TX,Tx_CLK);//TX_CLK1 = 1;
bitclr(PORT_TX, Tx_CLK);//TX_CLK1 = 0;
rf_address <<= 1;
}
//Clock in the data_array
for(i = 0 ; i < MAX_MESSAGE ; i++) //29 bytes
{
temp = TX_data_array[i];
for(j = 0 ; j < 8 ; j++) //One bit at a time
{
//TX_DATA = temp.7;
if (temp &0x80)
bitset(PORT_TX, Tx_DAT);
else
bitclr(PORT_TX, Tx_DAT);
bitset(PORT_TX, Tx_CLK);//TX_CLK1 = 1;
bitclr(PORT_TX, Tx_CLK);//TX_CLK1 = 0;
temp <<= 1;
}
}
//3. MCU sets CE low, this activates a nRF2401A ShockBurst™ transmission.
bitclr(PORT_TX,Tx_CE);//TX_CE = 0; //Start transmission
}
//2.4G Configuration - Receiver
//This setups up a RF-24G for receiving at 1mbps
void configure_receiver(void)
{
unsigned char i, j, temp;
unsigned char config_setup[14];
//During configuration of the receiver, we need RX_DATA as an output
PORTA = 0b00000000;
TRISA = 0b00000001; //0 = Output, 1 = Input (RX_DR is on RA0) (RX_DATA is on RA1)
//Config Mode
bitclr(PORT_RX,Rx_CE);//RX_CE = 0;
bitset(PORT_RX,Rx_CS);//RX_CS = 1;
//Setup configuration array
//===================================================================
//Data bits 111-104 Max data width on channel 1 (excluding CRC and adrs) is 232
config_setup[0] = 232;
//Data bits 103-64 Channel 2 address - we don't care, set it to 200
config_setup[1] = 0;
config_setup[2] = 0;
config_setup[3] = 0;
config_setup[4] = 0;
config_setup[5] = 200;
//Data bits 63-24 Channel 1 address - set it to 17
config_setup[6] = 0;
config_setup[7] = 0;
config_setup[8] = 0;
config_setup[9] = 0;
config_setup[10] = 17;
//Data bits 23-16 Address width and CRC
config_setup[11] = 0b00100011;
//Data bits 15-8
config_setup[12] = 0b01001101;
//Data bits 7-0
config_setup[13] = 0b00001101;
//===================================================================
//Clock in configuration data
for(i = 0 ; i < 14 ; i++)
{
temp = config_setup[i];
for(j = 0 ; j < 8 ; j++)
{
//RX_DATA = temp.7;
if (temp &0x80)
bitset(PORT_RX, Rx_DAT);
else
bitclr(PORT_RX, Rx_DAT);
bitset(PORT_RX,Rx_CLK);//RX_CLK1 = 1;
bitclr(PORT_RX,Rx_CLK);//RX_CLK1 = 0;
temp <<= 1;
}
}
//Configuration is actived on falling edge of CS (page 10)
bitclr(PORT_RX, Rx_CE);//RX_CE = 0;
bitclr(PORT_RX, Rx_CE);//RX_CS = 0;
//After configuration of the receiver, we need RX_DATA as an input
PORTA = 0b00000000;
TRISA = 0b00000011; //0 = Output, 1 = Input (RX_DR is on RA0) (RX_DATA is on RA1)
//Start monitoring the air
bitset(PORT_RX, Rx_CE);//RX_CE = 1;
bitclr(PORT_RX, Rx_CE);//RX_CS = 0;
#ifdef HI_TECH_C
#else
//printf("RX Configuration finished...\n\r", 0);
#endif
}
//2.4G Configuration - Transmitter
//This sets up one RF-24G for shockburst transmission
void configure_transmitter(void)
{
unsigned char i, j, temp;
unsigned char config_setup[14];
//Config Mode
bitclr(PORT_TX,Tx_CE);//TX_CE = 0;
bitset(PORT_TX,Tx_CS);//TX_CS = 1;
//Setup configuration array
//===================================================================
//Data bits 111-104 Max data width on channel 1 (excluding CRC and adrs) is 232
config_setup[0] = 232;
//Data bits 103-64 Channel 2 address - we don't care, set it to 200
config_setup[1] = 0;
config_setup[2] = 0;
config_setup[3] = 0;
config_setup[4] = 0;
config_setup[5] = 200;
//Data bits 63-24 Channel 1 address - set it to 17
config_setup[6] = 0;
config_setup[7] = 0;
config_setup[8] = 0;
config_setup[9] = 0;
config_setup[10] = 17;
//Data bits 23-16 Address width and CRC
config_setup[11] = 0b00100011;
//Data bits 15-8
config_setup[12] = 0b01001101;
//Data bits 7-0
config_setup[13] = 0b00001100;
//===================================================================
//Clock in configuration data
for(i = 0 ; i < 14 ; i++)
{
temp = config_setup[i];
for(j = 0 ; j < 8 ; j++)
{
//TX_DATA = temp.7;
if (temp&0x80)
bitset(PORT_TX, Tx_DAT);
else
bitclr(PORT_TX, Tx_DAT);
bitset(PORT_TX,Tx_CLK);//TX_CLK1 = 1;
bitclr(PORT_TX,Tx_CLK);//TX_CLK1 = 0;
temp <<= 1;
}
}
//Configuration is actived on falling edge of CS (page 10)
bitclr(PORT_TX,Tx_CE);//TX_CE = 0;
bitclr(PORT_TX,Tx_CS);//TX_CS = 0;
#ifdef HI_TECH_C
#else
//printf("TX Configuration finished...\n\r", 0);
#endif
}
#else
#pragma optimize 1
#pragma updateBank 0
void SendByte(unsigned char cmd)
{
unsigned char i;
//for(i = 0 ; i < 8 ; i++)
//{
// if (cmd&0x80)
// bitset(PORT_TX, Tx_MOSI);
// else
// bitclr(PORT_TX, Tx_MOSI);
// bitset(PORT_TX, Tx_SCK);
// bitclr(PORT_TX, Tx_SCK);
// cmd <<= 1;
//}
i = 8;
do {
PORT_TX.Tx_MOSI = cmd.7;
PORT_TX.Tx_SCK = 1;
PORT_TX.Tx_SCK = 0;
cmd <<= 1;
} while(--i);
}
#pragma updateBank 1
unsigned char GetCD(void)
{
unsigned char data, i;
data = 0;
#pragma updateBank 0
i = 8;
bitclr(PORT_TX, Tx_CSN);
SendByte(0x09); // read register 09 = PRD
do
{
data <<=1;
PORT_TX.Tx_SCK = 1;
//bitset(PORT_TX, Tx_SCK);
//if (bittest(PORT_RX,Rx_MISO))
// bitset(data,0);
data.0 = PORT_RX.Rx_MISO;
//bitclr(PORT_TX, Tx_SCK);
PORT_TX.Tx_SCK = 0;
} while(--i);
bitset(PORT_TX, Tx_CSN);
#pragma updateBank 1
return data;
//if (data)
// flGetCD = 1;
//else
// flGetCD = 0;
}
//unsigned char CDFound;
unsigned char CheckAir(unsigned char ttt)
{
int i;
//CDFound = 0xff;
OPTION = 3; // prescaler divide TMR0 rate by 8 for 8 MHz it will be 8mks (or 16 cicles)
TMR0 = 0;
while (TMR0 < ttt)
{
//GetCD();
if (GetCD())
{
return TMR0;
//break;
}
}
return 0xff;
}
//reset all ints
void receive_data(void)
{
uns8 i, j, data, /*cmd,*/ imax, iBitCount, iBitVal, iByteCount, data0;
bit data2, odd;
// send to serial output everything from buffer
while (RX_data_out != RX_data_len)
{
// needs to output message from a buffer
//TXREG = data;
//while(TXIF == 0);
if (TXIF == 0) // wait for next byte ready to transmit
{
}
else
{
if (RX_data_array[RX_data_out] != 0xff)
{
TXREG = RX_data_array[RX_data_out];
}
RX_data_out++;
if (RX_data_out >= (msRxlen+1))//MAX_MESSAGE_PLUS)
RX_data_out = 0;
}
}
if ((Config01 & 0x1c) != 0x10) // all case with no Carrier Detection
{
bitclr(PORT_TX, Tx_CSN);
//cmd = 0x61; //R_RX_PAYLOAD Read RX-payload: 1 – 32 bytes. A read operation
// always starts at byte 0. Payload is deleted from
// FIFO after it is read. Used in RX mode
SendByte(0x61);
imax = msRxlen;
switch(Config01&0x1c) // all modes except CRC = '1','2','3','4'
{
case 0x00:
break;
case 0x04: // this is a case ats9=lun012112233
if (Config01&0x40) // - needs to transfer data to computer
imax = 32;
break;
case 0x08:
imax = 30;
break;
case 0x0c:
imax = 30;
break;
case 0x10:
imax = 1;
break;
}
iBitCount = 0;
iBitVal = 0;
data = 0;
iByteCount = 0;
for (j = 0; j < imax; j++)//MAX_MESSAGE; j++)
{
for(i = 0 ; i < 8 ; i++)
{
bitset(PORT_TX, Tx_SCK);
switch(Config01 & 0x1c)
{
case 0x00: // '0' 250kbit chk sum
case 0x04: // '1' 250kbit no chk sum
data <<= 1;
if (bittest(PORT_RX,Rx_MISO))
bitset(data,0);
iByteCount++;
break;
case 0x08: // '2' 250kbit no chk sum 3 bit
if (bittest(PORT_RX,Rx_MISO))
iBitVal++;
iBitCount++;
if (iBitCount >= 3)
{ data <<= 1;
if (iBitVal >= 2)
bitset(data,0);
iBitCount = 0;
iBitVal = 0;
iByteCount++;
}
break;
case 0x0c: // '3' 250kbit no chk sum 5 bit
if (bittest(PORT_RX,Rx_MISO))
iBitVal++;
iBitCount++;
if (iBitCount >= 5)
{ data <<= 1;
if (iBitVal >= 3)
bitset(data,0);
iBitCount = 0;
iBitVal = 0;
iByteCount++;
}
break;
case 0x10: // '4' 250kbit no chk sum carrier detect
break;
}
bitclr(PORT_TX, Tx_SCK);
if (iByteCount >= 8)
{
iByteCount = 0;
if (Config01&0x40) // - needs to transfer data to computer
{
TXREG = data;
while(TXIF == 0);
}
else
{
RX_data_array[RX_data_len] = data;
RX_data_len ++;
if (RX_data_len >= (msRxlen+1))//MAX_MESSAGE_PLUS)
{
RX_data_len =0;
}
}
data = 0;
}
}
}
//RX_CSN = 1;
bitset(PORT_TX, Tx_CSN);
bitclr(PORT_TX, Tx_CSN);
//cmd = 0xE2; //FLUSH_RX Flush RX FIFO, used in RX mode
// Should not be executed during transmission of
// acknowledge, that is, acknowledge package will not be completed.
SendByte(0xe2);
bitset(PORT_TX, Tx_CSN);
bitclr(PORT_TX, Tx_CSN);
//data = 0x40;
//cmd = 0x27; // 001 0 0111 W_REGISTER to register 07 == STATUS
// 0100 0000 Write 1 to clear bit.
// 1 Data Ready RX FIFO interrupt. Asserted when new data arrives RX FIFOb.
// 0 Data Sent TX FIFO interrupt. Asserted when packet transmitted on TX.
// If AUTO_ACK is activated,this bit is set high only when ACK is received
// 0 Maximum number of TX retransmits interrupt
// Write 1 to clear bit. If MAX_RT is asserted it must be cleared
// to enable further communication.
//read 000 Data pipe number for the payload available for reading from
// RX_FIFO 000-101: Data Pipe Number 110: Not Used 111: RX FIFO Empty
// 0 TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO.
SendByte(0x27);
SendByte(0x40);
bitset(PORT_TX, Tx_CSN);
}
else // Carrier detection
{
delay_mks(26);
for(i =0; i < msTxlen; i++)
{
data = 0;
for (j = 0; j <4; j++)
{
data <<=1;
data0 = GetCD();//CheckAir(26);
data.0 = data0.0;
delay_mks(26);
}
RX_data_array[RX_data_len] = '0' + data;
RX_data_len ++;
if (RX_data_len >= (msRxlen+1))//MAX_MESSAGE_PLUS)
{
RX_data_len =0;
}
if (i == 3)
{
bitclr(PORT_TX,Tx_CE);
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq2);
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
}
}
//delay_mks(CD_IMP_LEN_HALF); // wait for half impuls
//delay_mks(200);
//delay_mks(200);
//delay_mks(200);
//bitclr(PORT_TX,Tx_CE);
//bitclr(PORT_TX,Tx_CSN);
//SendByte(0x25);
//SendByte(Freq2);
//bitset(PORT_TX, Tx_CSN);
//bitset(PORT_TX,Tx_CE);
//data = CheckAir(26);
//TXREG = (data >> 4) + '0';
//while(TXIF == 0);
//TXREG = (data & 0x0f) + '0';
//while(TXIF == 0);
//if (data < 100)
{
// //next will be on FQ3
// delay_mks(200);
// delay_mks(200);
//
// bitclr(PORT_TX,Tx_CE);
// bitclr(PORT_TX,Tx_CSN);
// SendByte(0x25);
// SendByte(Freq3);
// bitset(PORT_TX, Tx_CSN);
// bitset(PORT_TX,Tx_CE);
// data0 = CheckAir(26);
//TXREG = (data2 >> 4) + '0';
//while(TXIF == 0);
//TXREG = (data2 & 0x0f) + '0';
//while(TXIF == 0);
// TXREG = '~';
// while(TXIF == 0);
// TXREG = (data >> 4) + '0';
// while(TXIF == 0);
// TXREG = (data & 0x0f) + '0';
// while(TXIF == 0);
// TXREG = '^';
// while(TXIF == 0);
// data = data0;
// while(TXIF == 0);
// TXREG = (data >> 4) + '0';
// while(TXIF == 0);
// TXREG = (data & 0x0f) + '0';
//TXREG = CDFound + '0';
/*
if (CDFound < 46)
{
//TXREG = '-';
odd = 1;
data2 = 0;
for(i =0; i < msTxlen; i++)
{
data = 0;
for (j = 0; j <8; j++)
{
data <<=1;
bitclr(PORT_TX,Tx_CE);
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
if(data2)
{
SendByte(Freq3);
data2 = 0;
}
else
{
SendByte(Freq2);
data2 = 1;
}
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
//delay_mks(CD_IMP_LEN);
//GetCD();
CheckAir();
if (flGetCD) // get bit == 0
{
}
else
{
bitset(data, 0);
if (odd)
odd = 0;
else
odd = 1;
}
}
RX_data_array[RX_data_len] = data;
RX_data_len ++;
if (RX_data_len >= (msRxlen+1))//MAX_MESSAGE_PLUS)
{
RX_data_len =0;
}
}
bitclr(PORT_TX,Tx_CE);
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq3);
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
//delay_mks(CD_IMP_LEN);
//GetCD();
CheckAir();
if (flGetCD) // check stop bit
{
bitclr(PORT_TX,Tx_CE);
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
if (odd)
SendByte(Freq1);
else
SendByte(Freq2);
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
//delay_mks(CD_IMP_LEN);
//GetCD();
CheckAir();
if (flGetCD) // check odd bit
TXREG = '=';
else
TXREG = '#';
}
else
TXREG = '~';
}*/
}
// now restore FQ1 and continue receive
bitclr(PORT_TX,Tx_CE);
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq1);
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
}
}
//This sends out the data stored in the data_array
//data_array must be setup before calling this function
void transmit_data(void)
{
uns8 i, j, data, cmd, Freq, k;
bit data2;
bit odd;
//TX_CSN = 0;
bitclr(PORT_TX,Tx_CSN);
data = 0x7E; //clear previous ints======================================================================================
cmd = 0x27; // 001 0 0111 W_REGISTER to register 07 == STATUS
// 0111 1111 Write 1 to clear bit.
// 1 Data Ready RX FIFO interrupt. Asserted when new data arrives RX FIFOb.
// 1 Data Sent TX FIFO interrupt. Asserted when packet transmitted on TX.
// If AUTO_ACK is activated,this bit is set high only when ACK is received
// 1 Maximum number of TX retransmits interrupt
// Write 1 to clear bit. If MAX_RT is asserted it must be cleared
// to enable further communication.
//read 111 Data pipe number for the payload available for reading from
// RX_FIFO 000-101: Data Pipe Number 110: Not Used 111: RX FIFO Empty
// 1 TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO.
for(i = 0 ; i < 8 ; i++)
{
//TX_MOSI = cmd.7;
if (0x80&cmd)
bitset(PORT_TX,Tx_MOSI);
else
bitclr(PORT_TX,Tx_MOSI);
//TX_SCK = 1;
bitset(PORT_TX,Tx_SCK);
//data2 = TX_MISO;
data2 = 0;
if (bittest(PORT_RX, Rx_MISO))
data2 = 1;
//TX_SCK = 0;
bitclr(PORT_TX,Tx_SCK);
cmd <<= 1;
//while(TXIF == 0); //print out the status register before clearing stuff...==============================
//TXREG = data2+48;
}
//while(TXIF == 0);
//TXREG = 44;
//while(TXIF == 0);
//TXREG = 32;
SendByte(data);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
data = 0x5e;//0x3A; //PWR_UP = 1===========================================================================================
cmd = 0x20; // 001 0 0000 W_REGISTER to register 00000 == Configuration Register
// data in Configuration Register
// 0101 1110
// 1 MASK_RX_DR Mask interrupt caused by RX_DR
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect RX_DR as active low interrupt on the IRQ pin
// 0 MASK_TX_DS Mask interrupt caused by TX_DS
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect TX_DS as active low interrupt on the IRQ pin
// 1 MASK_MAX_RT Mask interrupt caused by MAX_RT
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect MAX_RT as active low interrupt on the IRQ pin
// 1 EN_CRC Enable CRC. Forced high if one of the bits in
// the EN_AA is high
// 1 CRCO CRC encoding scheme '0' - 1 byte '1' – 2 bytes
// 1 PWR_UP 1: POWER UP, 0:POWER DOWN
// 0 PRIM_RX RX/TX control 1: PRX, 0: PTX
SendByte(cmd);
SendByte(data);
bitset(PORT_TX,Tx_CSN);
if ((Config01 & 0x1c) != 0x10) // all case with no Carrier Detection
{
bitclr(PORT_TX,Tx_CSN);
//clear TX fifo===========================================================================================
//the data sheet says that this is supposed to come up 0 after POR, but that doesn't seem to be the case
cmd = 0xE1; // command FLUSH_TX= Flush TX FIFO, used in TX mode
SendByte(cmd);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
data2 = 0;
//data = TX_data_array[0];//0x34; //4 byte payload================================================================================
cmd = 0xA0; // W_TX_PAYLOAD Write TX-payload: 1 – 32 bytes. A write operation
// always starts at byte 0 used in TX payload
for(i = 0 ; i < 8 ; i++)
{
//TX_MOSI = cmd.7;
if (cmd&0x80)
bitset(PORT_TX, Tx_MOSI);
else
bitclr(PORT_TX, Tx_MOSI);
//TX_SCK = 1;
bitset(PORT_TX,Tx_SCK);
//data2 = TX_MISO;
data2 = 0;
if (bittest(PORT_RX, Rx_MISO))
data2 = 1;
//TX_SCK = 0;
bitclr(PORT_TX,Tx_SCK);
cmd <<= 1;
//while(TXIF == 0); //print out status register after clearing ints...===============================
//TXREG = data2+48;
}
//while(TXIF == 0);
//TXREG = 10;
//while(TXIF == 0);
//TXREG = 13;
//clock in payload==============================================================================================
switch(Config01 & 0x1c)
{
case 0x00: // '0' 2500kbit with chk sum
case 0x04: // '1' 250kbit no chk sum
for(i =0; i < msTxlen; i++)
{
SendByte(TX_data_array[i]);
}
break;
case 0x08: // '2' 250kbit 3 bits
for(i =0; i < msTxlen; i++)
{
data = TX_data_array[i];
for(j = 0 ; j < 8 ; j++)
{
if (data&0x80)
bitset(PORT_TX, Tx_MOSI);
else
bitclr(PORT_TX, Tx_MOSI);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
data <<= 1;
}
}
break;
case 0x0c: // '2' 250kbit 5 bits
for(i =0; i < msTxlen; i++)
{
data = TX_data_array[i];
for(j = 0 ; j < 8 ; j++)
{
if (data&0x80)
bitset(PORT_TX, Tx_MOSI);
else
bitclr(PORT_TX, Tx_MOSI);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
bitset(PORT_TX, Tx_SCK);
bitclr(PORT_TX, Tx_SCK);
data <<= 1;
}
}
break;
case 0x10: // '4' Carrier detection // we should not be here
break;
}
bitset(PORT_TX,Tx_CSN);
//Pulse CE to start transmission ========================================================================
//TX_CE = 1;
bitset(PORT_TX,Tx_CE);
//delay_ms(1);
//TX_CE = 0;
// IRQ must be fail to low on end of transmission
while(bittest(PORT_RX,Rx_IRQ)) //wait for finish transmission
{
}
bitclr(PORT_TX,Tx_CE);
}
else // transfer by switching carrier
{
// CE must be low at this moment of time??
// 1. Set PWR_UP = 1 and PRIM_RX = 0 in the CONFIG register.(done)
// 2. Wait 1.5ms PWR_UP->standby
//for(i =0; i < 8; i++)
//{
// delay_mks(25);
//}
// 3. In the RF register set:
// CONT_WAVE = 1.
// PLL_LOCK = 1.
// RF_PWR.
// register 06 RF_SETUP RF Setup Register
// CONT_WAVE 7 0 R/W Enables continuous carrier transmit when high.
// Reserved 6 0 R/W Only '0' allowed
// RF_DR_LOW 5 0 R/W Set RF Data Rate to 250kbps. See RF_DR_HIGH
// for encoding.
// PLL_LOCK 4 0 R/W Force PLL lock signal. Only used in test
// RF_DR_HIGH 3 1 R/W Select between the high speed data rates. This bit
// is don’t care if RF_DR_LOW is set.
// Encoding: [RF_DR_LOW, RF_DR_HIGH]:‘00’ – 1Mbps
// ‘01’ – 2Mbps ‘10’ – 250kbps ‘11’ – Reserved
// RF_PWR 2:1 11 R/W Set RF output power in TX mode '00' – -18dBm
// '01' – -12dBm '10' – -6dBm '11' – 0dBm
bitclr(PORT_TX,Tx_CSN);
//data = 0xb6;
//cmd = 0x26;// 00 10 0110 W_REGISTER to register 00006 == RF_SETUP RF Setup Register
// 1011 0110
// 1 CONT_WAVE Enables continuous carrier transmit when high.
// 0 Only '0' allowed
// 1 RF_DR_LOW Set RF Data Rate to 250kbps. See RF_DR_HIGH
// for encoding.
// 1 PLL_LOCK Force PLL lock signal. Only used in test
//
// 0 RF_DR_HIGH Select between the high speed data rates. This bit
// is don’t care if RF_DR_LOW is set.
// Encoding: [RF_DR_LOW, RF_DR_HIGH]:
// ‘00’ – 1Mbps ‘01’ – 2Mbps ‘10’ – 250kbps ‘11’ – Reserved
// 11 Set RF output power in TX mode '00' – -18dBm '01' – -12dBm
// '10' – -6dBm '11' – 0dBm
// 0 Don’t care
SendByte(0x26);
SendByte(0xb6);
bitset(PORT_TX,Tx_CSN);
// send initial FQ1+FQ2+
// 4. Set the wanted RF channel.
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq1);
bitset(PORT_TX, Tx_CSN);
// 5. Set CE high.
// 6. Keep CE high as long as the carrier is needed.
bitset(PORT_TX,Tx_CE);
delay_mks(182);
//delay_mks(200);
//delay_mks(200);
bitclr(PORT_TX,Tx_CE);
delay_mks(200);
// 4. Set the wanted RF channel.
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq2);
bitset(PORT_TX, Tx_CSN);
// 5. Set CE high.
// 6. Keep CE high as long as the carrier is needed.
bitset(PORT_TX,Tx_CE);
delay_mks(182);
//delay_mks(200);
//delay_mks(200);
bitclr(PORT_TX,Tx_CE);
// 4. Set the wanted RF channel.
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq3);
bitset(PORT_TX, Tx_CSN);
// 5. Set CE high.
// 6. Keep CE high as long as the carrier is needed.
bitset(PORT_TX,Tx_CE);
delay_mks(182);
//delay_mks(200);
//delay_mks(200);
bitclr(PORT_TX,Tx_CE);
/*
data2 = 0;
odd = 1;
for(i =0; i < msTxlen; i++)
{
data = TX_data_array[i];
for (j = 0; j <8; j++)
{
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
if (bittest(data,7))
{
SendByte(Freq1);
if (odd)
odd = 0;
else
odd = 1;
}
else
{
if (data2)
SendByte(Freq3);
else
SendByte(Freq2);
}
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
delay_mks(CD_IMP_LEN);
bitclr(PORT_TX,Tx_CE);
if (data2)
data2 = 0;
else
data2 = 1;
data<<=1;
}
}
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq3);
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
delay_mks(200);
bitclr(PORT_TX,Tx_CE);
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
if (odd)
SendByte(Freq1);
else
SendByte(Freq2);
bitset(PORT_TX, Tx_CSN);
bitset(PORT_TX,Tx_CE);
delay_mks(CD_IMP_LEN);
bitclr(PORT_TX,Tx_CE);
configure_common();
data2 = 0;
odd = 1;
for(i =0; i <= msTxlen; i++)
{
if ( i)
{
data = TX_data_array[i-1];
break;
}
for (j = 0; j <8; j++)
{
if (i == 0)
{
if (j == 0)
Freq = Freq1;
else
{
if (j == 1)
Freq = Freq2;
else
{
if (j == 2)
Freq = Freq3;
else
break;
}
}
}
else
{
if (bittest(data,7))
{
Freq = Freq1;
if (odd)
odd = 0;
else
odd = 1;
}
else
{
if (data2)
Freq = Freq3;
else
Freq = Freq2;
}
if (data2)
data2 = 0;
else
data2 = 1;
}
data<<=1;
bitclr(PORT_TX,Tx_CSN);
SendByte(0xE1);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq);
bitset(PORT_TX, Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
SendByte(0xA0);
for(k =0; k < MAX_MESSAGE; k++)
{
SendByte(TX_data_array[k]);
}
bitset(PORT_TX,Tx_CSN);
bitset(PORT_TX,Tx_CE);
while(bittest(PORT_RX,Rx_IRQ)) //wait for finish transmission
{
}
bitclr(PORT_TX,Tx_CE);
delay_mks(200);
}
}*/
bitclr(PORT_TX,Tx_CSN);
SendByte(0x25);
SendByte(Freq1);
bitset(PORT_TX, Tx_CSN);
}
}
void configure_common(void)
{
bitclr(PORT_TX,Tx_CE); // Chip Enable Activates RX or TX mode (now disable)
bitclr(PORT_TX,Tx_CSN);
//data = 0x01; //address width = 5======================================================================================
//cmd = 0x23; // 001 0 0001 W_REGISTER to register 00003 == SETUP_AW Setup of Address Widths
// (common for all data pipes)
// 0000 0001 RX/TX Address field width '00' - Illegal '01' - 3 bytes
// '10' - 4 bytes '11' – 5 bytes
SendByte(0x23);
SendByte(0x01);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
//data = 0x27; //data rate = 250KBit=================================================================================
//cmd = 0x26; // 00 10 0110 W_REGISTER to register 00006 == RF_SETUP RF Setup Register
// 0010 0111
// 0 CONT_WAVE Enables continuous carrier transmit when high.
// 0 Only '0' allowed
// 1 RF_DR_LOW Set RF Data Rate to 250kbps. See RF_DR_HIGH
// for encoding.
// 0 PLL_LOCK Force PLL lock signal. Only used in test
//
// 0 RF_DR_HIGH Select between the high speed data rates. This bit
// is don’t care if RF_DR_LOW is set.
// Encoding: [RF_DR_LOW, RF_DR_HIGH]:
// ‘00’ – 1Mbps ‘01’ – 2Mbps ‘10’ – 250kbps ‘11’ – Reserved
// 11 Set RF output power in TX mode '00' – -18dBm '01' – -12dBm
// '10' – -6dBm '11' – 0dBm
// 1 Don’t care
SendByte(0x26);
SendByte(0x27);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
//data = 0x02; //set channel 2, this is default but we did it anyway...====================================================
//cmd = 0x25; // 001 0 0101 W_REGISTER to register 00005 == RF Channel
// 0000 0010 Sets the frequency channel nRF24L01 operates on
SendByte(0x25);
SendByte(Freq1);
bitset(PORT_TX, Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
//data = 0xE7; //set address E7E7E7E7E7, also default...====================================================================
//cmd = 0x30; // 001 1 0000 W_REGISTER to register 00010 == TX_ADDR
SendByte(0x30);
SendByte(Addr1);
SendByte(Addr2);
SendByte(Addr3);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
//data = 0xE7; //set address E7E7E7E7E7, also default...====================================================================
//cmd = 0x2a; // 001 0 1010 W_REGISTER to register 00010 == RX_ADDR_0
SendByte(0x2a);
SendByte(Addr1);
SendByte(Addr2);
SendByte(Addr3);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX, Tx_CSN);
//disable auto-ack, RX mode===========================================================================================
//shouldn't have to do this, but it won't TX if you don't
//data = 0x00;
//cmd = 0x21; // 001 0 0001 W_REGISTER to register 00001 == EN_AA Enable ‘Auto Acknowledgment’ Function
// Disable this functionality to be compatible with nRF2401
// 0000 0000 - Enable auto acknowledgement data pipe 5-0 All disabled
SendByte(0x21);
SendByte(0x00);
bitset(PORT_TX,Tx_CSN); // SPI Chip Select
bitclr(PORT_TX,Tx_CSN);
//data = 0x00; //auto retransmit off===========================================================================================
//cmd = 0x24; // 001 0 0100 W_REGISTER to register 04 == SETUP_RETR
// 0000 0000
// 0000 Auto Retransmit Delay 0000 – 250µS 0001 – 500µS 1111 – 4000µS
// 0000 Auto Retransmit Count: 0000 –Re-Transmit disabled
// 0001 – Up to 1 Re-Transmit on fail of AA 0010
SendByte(0x24);
SendByte(0x00);
bitset(PORT_TX,Tx_CSN);
bitclr(PORT_TX,Tx_CSN);
//data = 0x04; //4 byte payload =======================================================================================
//cmd = 0x31; // 001 1 0001 W_REGISTER to register 00011 == RX_PW_P0
// 0000 0100
// 00 0100 Number of bytes in RX payload in data pipe 0 (1 to 32 bytes).
// 0 Pipe not used 1 = 1 byte …32 = 32 bytes
// for TX length defined by amount bytes clocked to RF24l01+
SendByte(0x31);
SendByte(msRxlen);//MAX_MESSAGE);//0x04);
bitset(PORT_TX,Tx_CSN);
}
//2.4G Configuration - Transmitter
//This sets up one RF-24G for shockburst transmission
void configure_transmitter(void)
{
//uns8 i, j, data, data2, cmd;
//data2 = 0;
bitclr(PORT_TX,Tx_CE); // Chip Enable De Activates RX or TX mode (from now it disable)
bitclr(PORT_TX,Tx_CSN); // SPI Chip Select
//cmd = 0x20;
//data = 0x3c; // PTX, CRC enabled, mask a couple of ints=============================================================
// 001 0 0000 W_REGISTER to register 00000 == Configuration Register
// data in Configuration Register
// 0011 1000
// 0 MASK_RX_DR Mask interrupt caused by RX_DR
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect RX_DR as active low interrupt on the IRQ pin
// 1 MASK_TX_DS Mask interrupt caused by TX_DS
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect TX_DS as active low interrupt on the IRQ pin
// 1 MASK_MAX_RT Mask interrupt caused by MAX_RT
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect MAX_RT as active low interrupt on the IRQ pin
// 1 EN_CRC Enable CRC. Forced high if one of the bits in
// the EN_AA is high
// 1 CRCO CRC encoding scheme '0' - 1 byte '1' – 2 bytes
// 0 PWR_UP 1: POWER UP, 0:POWER DOWN
// 0PRIM_RX RX/TX control 1: PRX, 0: PTX
SendByte(0x20);
SendByte(0x3e);//0x3c); ?? why not?
bitset(PORT_TX,Tx_CSN);
//configure_common();
}
//2.4G Configuration - receiver
//This sets up one RF-24G for shockburst reseiver
void configure_receiver(void)
{
uns8 data;
bitclr(PORT_TX,Tx_CE); // Chip Enable Activates RX or TX mode (now disable)
data = 0x3f;//0x3d; why not???
//cmd = 0x20; // 001 0 0000 W_REGISTER to register 00000 == Configuration Register
// data in Configuration Register
// 0011 1101
// 0 MASK_RX_DR Mask interrupt caused by RX_DR
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect RX_DR as active low interrupt on the IRQ pin
// 1 MASK_TX_DS Mask interrupt caused by TX_DS
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect TX_DS as active low interrupt on the IRQ pin
// 1 MASK_MAX_RT Mask interrupt caused by MAX_RT
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect MAX_RT as active low interrupt on the IRQ pin
// 1 EN_CRC Enable CRC. Forced high if one of the bits in
// the EN_AA is high
// 1 CRCO CRC encoding scheme '0' - 1 byte '1' – 2 bytes
// 0 PWR_UP 1: POWER UP, 0:POWER DOWN
// 1PRIM_RX RX/TX control 1: PRX, 0: PTX
if (Config01&0x1c) // all modes except CRC
{
bitclr(data, 3);
}
bitclr(PORT_TX,Tx_CSN); // SPI Chip Select
SendByte(0x20);
SendByte(data);
bitset(PORT_TX,Tx_CSN);
if (Config01&0x1c) // all modes except CRC
{
bitclr(PORT_TX,Tx_CSN);
//data = 0x04; //4 byte payload =======================================================================================
//cmd = 0x31; // 001 1 0001 W_REGISTER to register 00011 == RX_PW_P0
// 0000 0100
// 11 0010 Number of bytes in RX payload in data pipe 0 (1 to 32 bytes).
// 0 Pipe not used 1 = 1 byte …32 = 32 bytes
// for TX length defined by amount bytes clocked to RF24l01+
SendByte(0x31);
SendByte(32);//MAX_MESSAGE);//0x04);
bitset(PORT_TX,Tx_CSN);
}
//configure_common();
bitset(data,1);// = 0x3F; //PWR_UP = 1 ==============================================================================================
//cmd = 0x20; // 001 0 0000 W_REGISTER to register 00000 == Configuration Register
// data in Configuration Register
// 0011 1111
// 0 MASK_RX_DR Mask interrupt caused by RX_DR
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect RX_DR as active low interrupt on the IRQ pin
// 1 MASK_TX_DS Mask interrupt caused by TX_DS
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect TX_DS as active low interrupt on the IRQ pin
// 1 MASK_MAX_RT Mask interrupt caused by MAX_RT
// 1: Interrupt not reflected on the IRQ pin
// 0: Reflect MAX_RT as active low interrupt on the IRQ pin
// 1 EN_CRC Enable CRC. Forced high if one of the bits in
// the EN_AA is high
// 1 CRCO CRC encoding scheme '0' - 1 byte '1' – 2 bytes
// 1 PWR_UP 1: POWER UP, 0:POWER DOWN
// 1PRIM_RX RX/TX control 1: PRX, 0: PTX
bitclr(PORT_TX,Tx_CSN);
SendByte(0x20);
SendByte(data);
bitset(PORT_TX,Tx_CSN); // SPI Chip Select
bitset(PORT_TX,Tx_CE); // Chip Enable Activates RX or TX mode (now RX mode)
}
#endif